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carbon nanotube transistors achieve a leap in industrializat

Time:2020/06/15 丨 source:未知 丨 visit count:

A small improvement, more than 1100 times, carbon nanotube transistors achieve a leap in industrialization
 
Carbon nanotube transistors are one step closer to commercial reality, and now MIT researchers have demonstrated that these devices can be quickly manufactured in commercial equipment, the same equipment that makes silicon-based transistors that are the backbone of today's computing industry.
 
Carbon nanotube field-effect transistors (CNFETs) are more energy-efficient than silicon field-effect transistors (silicon field-effect) and can be used to manufacture new three-dimensional microprocessors. But so far, most of them exist in a "manual" space, only produced in small quantities in academic laboratories.
 
However, in a study published in "Nature Electronics" on June 1, scientists showed how to mass-produce CNFETs on 200mm wafers, which is the industry standard for computer chip design. CNFET was created in a commercial silicon manufacturing plant and a semiconductor foundry in the United States.
 
After analyzing the deposition technology used to fabricate CNFETs, MIT Assistant Professor of Electrical Engineering and Computer Science Max Shulaker and his colleagues made some changes that made the manufacturing process more than 1,100 times faster than traditional methods, and also reduced Cost of production. The technology is to deposit carbon nanotubes side by side on the wafer, and distribute them on multiple wafers through 14400 x 14400 array CFNETs.
 

 
Solve the problem of messy emissions
For decades, improvements in silicon-based transistor manufacturing technology have lowered prices and increased the energy efficiency of computing. However, with the increase in the number of transistors packaged into integrated circuits, it seems that energy efficiency has not been improved at a historical rate, and this trend may be coming to an end.
 
CNFETs are an attractive alternative technology because they are "an order of magnitude more energy efficient" than silicon-based transistors. Unlike silicon-based transistors manufactured at temperatures of about 450 to 500 degrees Celsius, CNFETs can also be manufactured at temperatures close to room temperature. This means that it is actually possible to build circuit layers directly on top of previously manufactured circuit layers to create three-dimensional chips. Silicon-based technology cannot do this because it will melt the underlying layer. One possible application in the future is a 3D computer chip that combines logic and storage functions, which is expected to beat the performance of the latest 2D chips made of silicon by advanced orders of magnitude.
 
One of the most effective ways to build CFNET in the laboratory is a method of depositing nanotubes, called incubation. In this method, the wafer is immersed in a nanotube bath until the nanotubes stick to the wafer surface. The incubation process of CNT is shown in Figure 1a. The substrate is pre-patterned with a partially embedded bottom metal gate, followed by high-k gate dielectric deposition. The wafer is then immersed in a tank containing a solution consisting of purified semiconductor CNT (≥99.99%) suspended in toluene. Immerse the wafer in the CNT suspension for a set period of time, then take it out, rinse with solvent spray and dry with nitrogen.
 

Figure 1. Characterization of carbon nanotube deposition incubation method
 
The performance of CNFETs depends largely on the deposition process, which affects the number and orientation of carbon nanotubes on the wafer surface. Perfect alignment of nanotubes in CNFETs can produce ideal performance, but it is difficult to achieve alignment. Because it is very difficult to perfectly place billions of tiny 1 nm diameter nanotubes on a 200 mm wafer in a perfect direction.
 
Although the incubation method is practical in industry, it is impossible to align the nanotubes at all. It's like the Wuhan hot dry noodles are placed on the disk in a mess. However, after their experiments, it was discovered that a simple incubation process would help produce CNFETs with better performance than silicon-based transistors.
 

Figure 2. Flowchart of the VLSI design and analysis process for EDP quantification of commercial-grade processors designed with CNFETs on a range of CNT densities
 
CNFETs outside the beaker
Careful observation of the incubation process shows how researchers can improve the process to make it more suitable for industrial production. Figures 3a, b illustrate an improved CNT incubation method, that is, "dry cycle" incubation, which utilizes the drying process to reduce the rate of desorption and tilts the balance to facilitate faster deposition. For dry cycle incubation, the substrate is immersed in the CNT solution and incubated for 10 s (using a fast, linear deposition method). The substrate was then removed from the solution, rinsed with solvent spray and dried with nitrogen. This process (a "single cycle" incubation) is then repeated multiple times. This method can significantly reduce the incubation time from 48 hours to 150 seconds.
 
Figure 3c shows another new method called ACE (Artificial Concentration by Evaporation) that deposits a small amount of nanotube solution on the wafer instead of immersing the wafer in the tank. The slow evaporation of the liquid increases the concentration of carbon nanotubes and the total density of the nanotubes deposited on the wafer.
 

Figure 3. New method to improve incubation
 
Why are these changes necessary? Because it is no problem to put the wafers in the beaker for a week in the laboratory, but for the company, it cannot afford such a luxurious process.
 
The researchers collaborated with commercial silicon manufacturing plant Analog Devices and semiconductor foundry SkyWater Technology to manufacture CNFETs using improved methods. They were able to use the same equipment used to manufacture silicon-based wafers in both factories, while also ensuring that the nanotube solution met the factory’s strict chemical and contaminant requirements. This partnership helped them develop automated, high-volume, low-cost processes.
 

Figure 4. Integrating CNFET into a commercial silicon foundry
 
The next work of the research group is already underway, which is to use CNFETs to build different types of integrated circuits in industrial environments, and to explore some new functions that 3D chips may provide. This is a very important step towards industrialization!
 
In summary, this article has reported the process of manufacturing CNFETs in a commercial silicon manufacturing facility, demonstrating wafer-level uniformity and repeatability of multiple 200mm wafers. By understanding the mechanism of CNT incubation, an improved process was developed, which significantly increased the flux and CNT density. In addition, it also shows that the CNT deposited through incubation can meet the requirements of the future CNFET technology that can be manufactured, compatible with silicon CMOS and high performance.
 
Reference link:
https://doi.org/10.1038/s41928-020-0419-7
 
Article from website
 
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